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ds007902-0708 preliminary product specification z16c30 cmos usc universal serial controller copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com
ds007902-0708 p r e l i m i n a r y do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this pu blication concerning the devices, applications, or technology describe d is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical an d mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ds007902-0708 p r e l i m i n a r y revision history z16c30 product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no july 2008 02 updated as per latest template and style guide. all jan 2000 01 original issue
ds007902-0708 p r e l i m i n a r y table of contents z16c30 product specification iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 temperature ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 usc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 data communications capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 character counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 baud rate generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 digital phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clock multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 i/o interface capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ds007902-0708 p r e l i m i n a r y architectural overview z16c30 product specification 1 architectural overview features the key features of zilog?s z16c30 device include: ? two independent 0-to-10 mbps full-duplex channels, each with two baud rate gener- ators and one digital phase-locke d loop (dpll) for clock recovery ? 32-byte data fifo?s for ea ch receiver and transmitter ? 110 ns bus cycle time, 16-bit data bus bandwidth ? multi-protocol operation under program cont rol with independent mode selection for receiver and transmitter ? async mode with 1 to 8 bits/character, 1/16 to 2 stop bits/character in 1/16-bit incre- ments, programmable clock fa ctor, break detect and generation, odd, even, mark, space or no parity and framing error detec tion, supports one addr ess/data bit and mil std 1553b protocols ? byte oriented synchronous mode with one to eight bits/character, programmable idle line condition, optional receive sync stripp ing; optional preamble transmission, 16- or 32-bit crc, and transmit -to-receive slaving (for x.21) ? bisync mode with 2- to 16-bit programmabl e sync character, pr ogrammable id le line condition, optional receive sync stripping, optional preamble transmission, 16- or 32- bit crc ? transparent bisync mode with ebcdic or ascii character code, automatic crc han- dling, programmable idle li ne condition, optional preamble transmission, automatic recognition of dle, syn, soh, itx, etx, etb, eot, enq, and itb ? external character sync mode for receive ? hdlc/sdlc mode with eight-bit address compare, extended address field option, 16- or 32-bit crc, programmable idle line condition, optional preamble transmission and loop mode ? dma interface with separate request and acknowledge for each receiver and transmit- ter ? channel load command for dma controlled initialization ? flexible bus interface for direct connection to most microprocessors, user programma- ble for 8 or 16 bits wide, directly supports 680x0 family or 8x86 family bus interfaces ? low power cmos ? 68-pin plcc/100-pin vqfp packages
ds007902-0708 p r e l i m i n a r y architectural overview z16c30 product specification 2 general description zilog?s z16c30 usc universal serial contro ller is a dual-channel multi-protocol data communications peripheral designed for u se with any conventional multiplexed or non- multiplexed bus. the usc functions as a seria l-to-parallel, parallel-to-serial converter/ controller and may be software configured to satisfy a wide variety of serial communica- tions applications. the device contains a vari ety of new, sophisticated internal functions including two baud rate generators per channe l, one digital phase-lock ed loop (dpll) per channel, character counters for both receive an d transmit in each ch annel and 32-byte data fifo?s for each receiver and transmitter ( figure 1 on page 3). zilog now offers a high speed version of the usc with improved bus bandwidth. cpu bus accesses have been shortened from 160 ns per access to 110 ns per access. the usc has a transmit and receive clock range of up to 10 mhz (20 mhz when using the dpll, brg, or ctr) and data transfer rates as high as 10 mbits/sec full duplex. the usc handles asynchronous formats, s ynchronous byte-oriented formats such as bisync, and synchronous bit-oriented format s such as hdlc. this device supports vir- tually any serial data transfer application. the device can generate an d check crc in any synchron ous mode and can be pro- grammed to check data integrity in various modes. the usc also has facilities for modem controls in both channels. in applications where these cont rols are not needed, the modem controls may be used for gene ral-purpose i/o (gpio). the same is true for most of the other pins in each channel. interrupts are supported with a daisy-chain hi erarchy, with the two channels having com- pletely separate interrupt structures. high-speed data transfers through dma are supported by a request/acknowledge signal pair for each receiver and tr ansmitter. the device supports automatic status transfer through dma and also allows devi ce initialization under dma control. when written to, all reserved bits must be programmed to 0. to aid in efficiently programming the usc, support tools are available. the technical manual describes in detail all features present ed in this product specification and gives programming sequence hints. the programmer? s assistant is a ms-dos disk-based pro- gramming initialization tool to be used in conjunction with the technical manual. there are also available assorted application notes and development boards to assist in the hard- ware/software development. all signals with an overline , are active low. for example: b/w , in which word is active low, and b /w, in which byte is active low. power connections follow th ese conventional descriptions: note:
ds007902-0708 p r e l i m i n a r y architectural overview z16c30 product specification 3 table 1. power connection conventions connection circuit device power v cc v dd ground gnd v ss figure 1. z16c30 block diagram to other channel receive receive fifo interrupt control channel control transmit fifo transmit dma i/o data buffer cpu (32 byte) control dma (32 byte) control receive data receiver receive/ transmit clocks transmitter transmit data clock mux 1. dpll 2. counters 3. brg0 4. brg1 i/o and device status
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 4 pin description figure 2. z16c30 pin functions ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 as ds rd wr cs a/b d/c r/w pitack sitack wait /rdy v ss v ss v ss v ss v ss v ss v ss txda rxda txca rxca ctsa dcda rxreqa rxacka txreqa txacka inta ieia ieoa txdb rxdb serial data channel clocks channel i/o channel dma interface reset device txcb rxcb ctsb dcdb rxreqb rxackb txreqb txackb intb ieib ieob reset v dd v dd v dd v dd v dd v dd v dd channel interrupt interface ground interrupt control bus timing address/ data bus serial data channel clocks channel i/o channel dma interface channel interrupt interface power
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 5 figure 3. z16c30 68-pin plcc pin assignments 60 44 10 26 rxacka inta ieia ieoa gnd v cc ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd v cc rxreqa txacka wait/ rdy sitack a/ b d/ c cs reset v cc v cc v cc as ds rd wr r/ w pitack txackb 43 27 61 9 68-pin plcc 1 rxack b intb ieib ieob gnd v cc ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 gnd v cc rxreqb txreqa rxca rxda dcda txca txda ctsa gnd gnd gnd ctsb txdb txcb dcdb rxdb rxcb txreqb
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 6 the z16c30 contains 13 pins per channel for channel i/o, 16 pins for address and data, 12 pins for cpu handshake, and 14 pins for power and ground. three separate bus interface types are availa ble for the device. the bus configuration register (bcr) and external co nnections to the ad bus contro l selection of the bus type. a 16-bit bus is selected by setting bcr bit 2 to a 1. the 8-bit bus is selected by setting bcr bit 2 to 0 and tying ad15?ad8 to v ss . figure 4. 100-pin vq fp pin assignments 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 nc nc nc nc txackb pitack r/w wr rd ds as v cc v cc v cc reset cs d/c a/b sitack wait /rdy txacka nc nc nc nc nc nc nc nc txreqb rxcb rxdb dcdb txcb txdb ctsb gnd gnd gnd ctsa txda txca dcda rxda rxca txreqa nc nc nc nc rxacka inta ieia ieoa gnd v cc ad0 nc nc nc nc ad1 ad2 ad3 nc nc nc nc ad4 ad5 ad6 ad7 gnd v cc rxreqa rxackb intb ieib ieob gnd v cc ad8 nc nc nc nc ad9 ad10 ad11 nc nc nc nc ad12 ad13 ad14 ad15 gnd v cc rxreqb 510152025 70 65 60 55 51 75 100-pin vqfp
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 7 the 8-bit bus with separate address is selected by setting bcr bit 2 to 0 and, during the bcr write, forcing ad15 to a 1 and forcing ad14?ad8 to 0. the multiplexed bus is selected for the usc if th ere is an address strobe prior to or during the transaction which writes the bcr. if no addr ess strobe is present prior to or during the transaction which writes the bcr, a nonmultiplexed bus is selected (see figure 29 on page 49). pin functions reset reset (input, active low)? this signal resets the de vice to a known state. the first write to the usc after a reset accesses the bcr to select additional bus op tions for the device. as address strobe (input, active low)? this signal is used in the multiplexed bus modes to latch the address on the ad lines. the as signal is not used in the nonmulti- plexed bus modes and should be tied to v dd . ds data strobe (input, active low)? this signal strobes data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle. ds also strobes data into the device on the state of r/w . rd read strobe (input, active low)? this signal strobes data out of the device during a read and may strobe an interrupt vector out of the device during an interrupt acknowledge cycle. wr write strobe (input, active low)? this signal strobes data into the device during a write. r/w read/write (input)? this signal determines the directio n of data transfer for a read or write cycle in conjunction with ds . cs chip select (input, active low)? this signal selects the device for access and must be asserted for read and write cycles, but is ignored during interrupt acknowledge and fly- by dma transfers. in the case of a multiplexed bus interface, cs is latched by the rising edge of as . a/b channel a/channel b select (input)? this signal selects between the two channels in the device. high selects channel a and low selects channel b. this signal is sampled and the result is latched during the bcr (bus configuration register) write. it programs the sense of the wait /rdy signal appropriate for different bus interfaces. d/c data/control select (input)? this signal, when high, pr ovides for direct access to the rdr and tdr. in the case of a multiplexed bus interface, d/ c high overrides the address provided to the device. sitack status interrupt acknowledge (input, active low)? this signal is a status sig- nal that indicates that an inte rrupt acknowledge cycle is in pr ogress. the device is capable of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. this signal is compatible with 680x0 family microproces- sors.
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 8 pitack pulsed interrupt acknowledge (input, active low)? this signal is a strobe signal that indicates that an interrupt acknow ledge cycle is in progress. the device is capa- ble of returning an interrupt vector that may be encoded with the type of interrupt pending during this acknowledge cycle. pitack may be programmed to accept a single pulse or double pulse ackn owledge type. this programming is done in the bcr. with the double pulse type selected, the first pitack is recognized bu t no action takes place. the interrupt vector is returned on the second pulse if th e no vector option is not selected. the double pulse type is compatible with 8x86 family microprocessors. wait /rdy wait/data ready (output, active low)? this signal serves to indicate when the data is available during a read cycle, when the device is ready to receive data during a write cycle, and when a valid vector is availa ble during an interrupt acknowledge cycle. it may be programmed to function either as a wait signal or a ready sign al using the state of the a/ b pin during the bcr write. when a/b is high during the bcr write, this signal functions as a wait output and thus support s the ready function of 8x86 family micro- processors. when a/b is low during the bcr write, this signal functions as a ready out- put and thus supports the dtack func tion of 680x0 family microprocessors. ad15?ad0 address/data bus (bidirectional, active high, tri-state)? the ad signals carry addresses to, and data to and from, the device. when the 16-b it nonmultiplexed bus is selected, ad15?ad0 carry data to and fro m the device. addresses are provided using a pointer within the device that is loaded w ith the desired register address. when selecting the 8-bit nonmultiplexed bus (without separate address) only ad7?ad0 are used to trans- fer data. the pointer is used for addressing, with ad15?ad8 unused. when selecting the 8-bit nonmultiplexed bus (with se parate address), ad7?ad0 are us ed to transfer data with ad15?ad8 used as address bu s. when the 16-bit multiplexe d bus is selected, addresses are latched from ad7?ad0 and data transfers are sixteen bits wide. when selecting the 8- bit multiplexed bus (without separate addre ss) only ad7?ad0 are used to transfer addresses and data, with ad1 5?ad8 unused. when the 8-b it multiplexed bus with sepa- rate address is selected, only ad7?ad0 are u sed to transfer data, while ad15?ad8 are used as an address bus. inta , intb interrupt request (outputs, active low)? these signals indicate that the channel has an interrupt condition pending and is requesting service. these outputs are not open-drain. ieia, ieib interrupt enable in (inputs, active high)? the iei signal for each channel is used with the accompanying ieo signal to fo rm an interrupt daisy chain. an active iei indicates that no device having higher priority is requesting or servicing an interrupt. ieoa, ieob interrupt enable out (outputs, active high)? the ieo signal for each channel is used with th e accompanying iei signal to form an interrupt daisy chain. ieo is low if iei is low, an interrupt is under service in the channe l, or an interrupt is pending during an interrupt acknowledge cycle. txacka , txackb transmit acknowledge (inputs or outputs, active low)? the pri- mary function of these signals is to perform fly-by dma transfers to the transmit fifos. they may also be used as bit inputs or outputs.
ds007902-0708 p r e l i m i n a r y pin description z16c30 product specification 9 rxacka , rxackb receive acknowledge (inputs or outputs, active low)? the pri- mary function of these signals is to perform fly-by dma transfers from the receive fifos. they may also be used as bit inputs or outputs. txda, txdb transmit data (outputs, active high, tri-state)? these signals carry the serial transmit data for each channel. rxda, rxdb receiv e data (inputs, active high)? these signals carry the serial receive data for each channel. txca , txcb transmit clock (inputs or outputs, active low)? these signals are used as clock inputs for any of the functional blocks within the device. they may also be used as outputs for various transmitter si gnals or internal clock signals. rxca , rxcb receive clock (inputs or outputs, active low)? these signals are used as clock inputs for any of the functional blocks within the device. they may also be used as outputs for various receiver sign als or internal clock signals. txreqa , txreqb transmit request (inputs or outputs, active low)? the primary function of these signals is to request dma tran sfers to the transmit fifos. they may also be used as simple inputs or outputs. rxreqa , rxreqb receive request (inputs or outputs, active low)? the primary function of these signals is to request dma transfers from the receive fifos. they may also be used as simple inputs or outputs. ctsa , ctsb clear to send (inputs or outputs, active low)? these signals are used as enables for the respective transmitters. they may also be programmed to generate inter- rupts on either transition or u sed as simple inputs or outputs. dcda , dcdb data carrier detect (inputs or outputs, active low)? these signals are used as enables for the respective receivers. they may also be programmed to generate interrupts on either transition or u sed as simple inputs or outputs.
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 10 electrical characteristics stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only; operation of the device at any condition above those indicated in the operational secti ons of these specifications is not implied. exposure to absolute maximu m rating conditions for extended periods may affect device reliability. standard test conditions the dc characteristics and capacitance sec tion below apply for th e following standard test conditions, unless otherwise noted. all vo ltages are referenced to gnd. positive cur- rent flows into the referenced pin ( figure 5 on page 11). standard conditions are as fol- lows: ? +4.5 v < v cc < +5.5 v ? gnd = 0 v ? t a as specified in ordering information on page 97 table 2. absolute maximum ratings symbol description min max units v cc supply voltage (*) ?0.3 +7.0 v t stg storage temp. ?65 +150 c t a oper ambient te m p ?c power dissipation 2.2 w * voltage on all pins with respect to gnd. ? see ordering information on page 97.
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 11 capacitance miscellaneous transistor count: 174,000 temperature ratings standard = 0 c to 70 c extended = ?40 c to +85 c figure 5. test load diagram table 3. capacitance symbol parameter min max unit condition c in input capacitance 10 pf unmeasured pins c out output capacitance 15 pf returned to ground. ci/o bidirectional capacitance 20 pf note: f = 1 mhz over specified temperature range. from pin 50 pf c l i ol i oh v ol max +v oh min 2
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 12 dc characteristics ac characteristics table 4. z16c30 dc characteristics symbol parameter min typ max unit condition v ih input high voltage 2.2 v cc +0.3 v v il input low voltage ?0.3 0.8 v v oh1 output high voltage 2.4 v i oh = ?1.6 ma v oh2 output high voltage v cc ?0.8 v i oh = ?250 a v ol output low voltage 0.4 v i ol = +2.0 ma i il input leakage 10.00 a 0.4 < v in < +2.4 v i ol output leakage 10.00 a 0.4 < v out < +2.4 v i ccl v cc supply current 750mav cc = 5 v v ih = 4.8 v v il = 0.2v note: v cc = 5 v 10% unless otherwise specified, over specified temperature range. table 5. z16c30 ac characteristics no symbol parameter min max units note 1 tcyc bus cycle time 110 ns 2 twasl as low width 30 ns 3 twash as high width 60 ns 4 twdsl ds low width 60 ns 5 twdsh ds high width 50 ns 6 tdas(ds) as rise to ds fall delay time 5ns 7 tdds(as) ds rise to as fall delay time 5ns 8 tdds(dra) ds fall to data active delay 0 ns 9 tdds(drv) ds fall to data valid delay 60 ns 10 tdds(drn) ds rise to data not valid delay 0ns 11 tdds(drz) ds rise to data float delay 20 ns
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 13 12 tscs(as) cs to as rise setup time 15 ns 13 thcs(as) cs to as rise hold time 5 ns 14 tsadd(as) direct address to as rise setup time 15 ns 1 15 thadd(as) direct address to as rise hold time 5ns1 16 tssia(as) sitack to as rise setup time 15 ns 17 thsia(as) sitack to as rise hold time 5ns 18 tsad(as) address to as rise setup time 15 ns 19 thad(as) address to as rise hold time 5ns 20 tsrw(ds) r/w to ds fall setup time 0 ns 21 thrw(ds) r/w to ds fall hold time 25 ns 22 tsdsf(rrq) ds fall to rxreq inactive delay 60 ns 4 23 tddsr(rrq) ds rise to rxreq active delay 0ns 24 tsdw(ds) write data to ds rise setup time 30 ns 25 thdw(ds) write data to ds rise hold time 0ns 26 tddsf(trq) ds fall to txreq inactive delay 65 ns 5,6 27 tddsr(trq) ds rise to txreq active delay 0ns 28 twrdl rd low width 60 ns 29 twrdh rd high width 50 ns 30 tdas(rd) as rise to rd fall delay time 5ns 31 tdrd(as) rd rise to as fall delay time 5ns 32 tdrd(dra) rd fall to data active delay 0 ns 33 tdrd(drv) rd fall to data valid delay 60 ns 34 tdrd(drn) rd rise to data not valid delay 0ns table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 14 35 tdrd(drz) rd rise to data float delay 20 ns 36 tdrdf(rrq) rd fall to rxreq inactive delay 60 ns 4 37 tdrdr(rrq) rd rise to rxreq active delay 0ns 38 twwrl wr low width 60 ns 39 twwrh wr high width 50 ns 40 tdas(wr) as rise to wr fall delay time 5ns 41 tdwr(as) wr rise to as fall delay time 5ns 42 tsdw(wr) write data to wr rise setup time 30 ns 43 thdw(wr) write data to wr rise hold time 0ns 44 tdwrf(trq) wr fall to txreq inactive delay 65 ns 5 45 tdwrr(trq) wr rise to txreq active delay 0ns 46 tscs(ds) cs to ds fall setup time 0 ns 2 47 thcs(ds) cs to ds fall hold time 25 ns 2 48 tsadd(ds) direct address to ds fall setup time 5ns1,2 49 thadd(ds) direct address to ds fall hold time 25 ns 1,2 50 tssia(ds) sitack to ds fall setup time 5ns2 51 thsia(ds) sitack to ds fall hold time 25 ns 2 52 tscs(rd) cs to rd fall setup time 0 ns 2 53 thcs(rd) cs to rd fall hold time 25 ns 2 54 tsadd(rd) direct address to rd fall setup time 5ns1,2 55 thadd(rd) direct address to rd fall hold time 25 ns 1,2 56 tssia(rd) sitack to rd fall setup time 5ns2 57 thsia(rd) sitack to rd fall hold time 25 ns 2 58 tscs(wr) cs to wr fall setup time 0 ns 2 table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 15 59 thcs(wr) cs to wr fall hold time 25 ns 2 60 tsadd(wr) direct address to wr fall setup time 5ns1,2 61 thadd(wr) direct address to wr fall hold time 25 ns 1,2 62 tssia(wr) sitack to wr fall setup time 5ns2 63 thsia(wr) sitack to wr fall hold time 25 ns 2 64 twrakl rxack low width 60 ns 65 twrakh rxack high width 50 ns 66 tdrak(dra) rxack fall to data active delay 0ns 67 tdrak(drv) rxack fall to data valid delay 60 ns 68 tdrak(drn) rxack rise to data not valid delay 0ns 69 tdrak(drz) rxack rise to data float delay 20 ns 70 tdrakf(rrq) rxack fall to rxreq inactive delay 60 ns 4 71 tdrakr(rrq) rxack rise to rxreq active delay 0ns 72 twtakl txack low width 60 ns 73 twtakh txack high width 50 ns 74 tsdw(tak) write data to txack rise setup time 30 ns 75 thdw(tak) write data to txack rise hold time 0ns 76 tdtakf(trq) txack fall to txreq inactive delay 65 ns 5 77 tdtakr(trq) txack rise to txreq active delay 0ns 78 tddsf(rdy) ds fall (intack) to rdy fall delay 200 ns 79 tdrdy(drv) rdy fall to data valid delay 40 ns 80 tddsr(rdy) ds rise to rdy rise delay 40 ns table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 16 81 tsiei(dsi) iei to ds fall (intack) setup time 10 ns 82 thiei(dsi) iei to ds rise (intack) hold time 0ns 83 tdiei(ieo) iei to ieo delay 30 ns 84 tdas(ieo) as rise (intack) to ieo delay 60 ns 85 tddsi(int) ds fall (intack) to int inactive delay 200 ns 7 87 tddsi(wr) ds fall (intack) to wait rise delay 200 ns 88 tdw(drv) wait rise to data valid delay 40 ns 89 tdrdf(rdy) rd fall (intack) to rdy fall delay 200 ns 90 tdrdr(rdy) rd rise to rdy rise delay 40 ns 91 tsiei(rdi) iei to rd fall (intack) setup time 10 ns 92 thiei(rdi) iei to rd rise (intack) hold time 0ns 93 tdrdi(int) rd fall (intack) to int inactive delay 200 ns 94 tdrdi(wf) rd fall (intack) to wait fall delay 40 ns 95 tdrdi(wr) rd fall (intack) to wait rise delay 200 ns 96 twpial pitack low width 60 ns 97 twpiah pitack high width 50 ns 98 tdas(pia) as rise to pitack fall delay time 5ns 99 tdpia(as) pitack rise to as fall delay time 5ns 100 tdpia(dra) pitack fall to data active delay 0ns 101 tdpia(drn) pitack rise to data not valid delay 0ns 102 tdpia(drz) pitack rise to data float delay 20 ns table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 17 103 tsiei(pia) iei to pitack fall setup time 10 ns 104 thiei(pia) iei to pitack rise hold time 0ns 105 tdpia(ieo) pitack fall to ieo delay 60 ns 106 tdpia(int) pitack fall to int inactive delay 200 ns 107 tdpiaf(rdy) pitack fall to rdy fall delay 200 ns 108 tdpiar(rdy) pitack rise to rdy rise delay 40 ns 109 tdpia(wf) pitack fall to wait fall delay 40 ns 110 tdpia(wr) pitac k fall to wait rise delay 200 ns 111 tdsia(int) sitack fall to ieo inactive delay 200 ns 2 112 twstbh strobe high width 50 ns 3 113 twresl reset low width 170 ns 114 twresh reset high width 60 ns 115 tdres(stb) reset rise to stb fall 60 ns 3 116 tddsf(rdy) ds fall to rdy fall delay 50 ns 117 tdwrf(rdy) wr fall to rdy fall delay 50 ns 118 tdwrr(rdy) wr rise to rdy rise delay 40 ns 119 tdrdf(rdy) rd fall to rdy fall delay 50 ns 120 tdrakf(rdy) rxack fall to rdy fall delay 50 ns 121 tdrakr(rdy) rxack rise to rdy rise delay 40 ns 122 tdtakf(rdy) txack fall to rdy fall delay 50 ns table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 18 usc timing the usc interface timing is similar to that fo und on a static ram, except that it is much more flexible. up to eight separate timing stro be signals may be present on the interface: ds , rd , wr , pitack , rxacka , rxackb , txacka, and txackb . only one of these timing strobes may be active at any time. should the external logic activate more than one of these strobes at the same time the usc will enter a pre-reset state that is only exited by a hardware reset. do not allow overlap of timing strobes. the timing diagrams beginning on the next page illustrate the differ ent bus transactions possible with the neces- sary setup hold and delay times. 123 tdtakr(rdy) txack rise to rdy rise delay 40 ns notes 1. direct address is any of a/b , d/c , or ad15?ad8 used as an address bus. 2. the parameter applies only when as is not present. 3. strobe (stb ) is any of ds , rd , wr , pitack , rxack or txac k. 4. parameter applies only if read empties the receive fifo. 5. parameter applies only if wr ite fills the transmit fifo. 6. for extended temperature part tddsi(wf) max = 220 ns. 7. for extended temperature part tddsf(trq) max = 75 ns. figure 6. reset timing table 5. z16c30 ac characteristics (continued) no symbol parameter min max units note reset stb note: stb is any of ds , rd , wr , pitack , rxack , or txack 113 114 115
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 19 figure 7. bus cycle timing figure 8. dma read cycle stb 112 1 1 64 65 66 67 68 69 70 71 120 79 121 rxack ad15?ad0 rxreq wait /rdy (wait) wait /rdy (ready) note: stb is any of ds , rd , wr , pitack , rxack , or txack
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 20 figure 9. dma write cycle 72 73 74 75 76 77 122 123 txack ad15?ad0 txreq wait /rdy (wait) wait /rdy (ready)
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 21 figure 10. multiplexed ds read cycle 12 13 14 15 16 17 2 6 1 3 7 20 21 4 5 18 19 8 9 10 11 22 23 116 79 80 cs a/b , d/c ack as r/w ds ad15?ad0 rxreq wait /rdy (wait) wait /rdy (ready)
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 22 figure 11. multiplexed ds write cycle cs a/b , d/c sitack as r/w ds ad15?ad0 txreq wait /rdy (wait) wait /rdy (ready) 12 13 14 15 16 17 2 6 1 7 20 21 4 5 18 19 24 25 26 27 116 80
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 23 figure 12. multiplexed rd read cycle cs a/b , d/c sitack as rd ad15?ad0 rxreq wait /rdy (wait) wait /rdy (ready) 12 13 14 15 16 17 2 30 1 31 28 18 19 36 37 119 90 cs 29 32 33 34 35 79
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 24 figure 13. multiplexed wr write cycle a/b , d/c sitack as wr ad15?ad0 txreq wait /rdy (wait) wait /rdy (ready) cs 12 13 14 15 16 17 2 40 1 41 38 39 18 19 42 43 44 45 117 118
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 25 figure 14. nonmultiplexed ds read cycle a/b , d/c sitack as wr ad15?ad0 txreq wait /rdy (wait) wait /rdy (ready) cs 12 13 14 15 16 17 2 40 1 41 38 39 18 19 42 43 44 45 117 118
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 26 figure 15. nonmultiplexed ds write cycle a/b , d/c sitack r/w ds ad15?ad0 txreq wait /rdy (wait) wait /rdy (ready) cs 46 47 48 49 50 51 20 21 4 5 1 24 25 26 27 116 80
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 27 figure 16. nonmultiplexed rd read cycle a/b , d/c sitack rd ad15?ad0 rxreq wait /rdy (ready) wait /rdy (ready) cs wait /rdy (wait) 52 53 54 55 56 57 28 1 29 32 33 34 35 36 37 119 79 90
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 28 figure 17. nonmultiplexed wr write cycle a/b , d/c sitack wr ad15?ad0 txreq wait /rdy (ready) cs wait /rdy (wait) 58 59 60 62 63 61 38 1 39 42 43 44 117 118 45
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 29 figure 18. multiplexed ds interrupt acknowledged cycle sitack ds ad15?ad0 wait /rdy (ready) as wait /rdy (wait) iei ieo int 2 6 7 17 16 4 5 18 19 8 86 10 11 87 88 79 78 80 81 82 83 84 85
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 30 figure 19. multiplexed rd interrupt acknowledge cycle sitack rd ad15?ad0 wait /rdy (ready) as wait /rdy (wait) iei ieo int 2 30 31 16 17 28 29 18 19 32 94 34 35 88 79 95 89 90 91 92 83 84 93
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 31 figure 20. multiplexed pulsed interrupt acknowledge cycle as pitack ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int 2 98 1 99 96 97 18 19 100 109 101 102 110 88 79 107 108 103 104 83 105 106
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 32 figure 21. nonmultiplexed ds interrupt acknowledge cycle ds sitack ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int 50 51 4 5 1 8 10 11 86 87 88 79 78 80 81 82 83 111 85
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 33 figure 22. nonmultiplexed rd interrupt acknowledge cycle rd sitack ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int 50 51 4 5 1 8 10 11 86 87 88 79 78 80 81 82 83 111 85
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 34 figure 23. nonmultiplexed pulsed interrupt acknowledge cycle sitack ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int pitack 96 97 1 79 107 100 101 102 108 103 104 83 106 105 109 88 110
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 35 figure 24. multiplexed double-pulse intack cycle ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int pitack (2-pulse) as 2 98 99 2 98 99 1 1 96 97 96 97 18 19 18 19 100 101 102 107 79 108 83 109 110 88 104 103 105 106
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 36 figure 25. nonmultiplexed double-pulse intack cycle ad15?ad0 wait /rdy (wait) wait /rdy (ready) iei ieo int pitack (2-pulse) 96 1 97 96 97 1 100 101 102 107 79 108 109 110 88 103 104 83 105 106
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 37 ac characteristics table 6 lists z16c30 general timing. table 6. z16c30 general timing no symbol parameter min max units notes 1 tsrxd(rxcr) rxd to rxc rise setup time (x1 mode) 0 ns 1 2 thrxd(rxcr) rxd to rxc rise hold time (x1 mode) 40 ns 1 3 tsrxd(rxcf) rxd to rxc fall setup time (x1 mode) 0 ns 1,3 4 thrxd(rxcf) rxd to rxc fall hold time (x1 mode) 40 ns 1,3 5 tssy(rxc) dcd as sync to rxc rise setup time 0 ns 1 6 thsy(rxc) dcd as sync to rxc rise hold time (x1 mode) 40 ns 1 7tdtxcf(txd)txc fall to txd delay 50 ns 2 8 tdtxcr(txd) txc rise to txd delay 50 ns 2,3 9 twrxch rxc high width 40 ns 1 11 tcrxc rxc cycle time 100 ns 1 12 twtxch txc high width 40 ns 2 13 twtxcl txc low width 40 ns 2 14 tctxc txc cycle time 100 ns 2 15 twext dcd or cts pulse width 70 ns 16 twsy dcd as sync input pulse width 70 ns 17 twclkh clk high width 20 ns 4 18 twclki clk high width 20 ns 4 19 tcclk clk cycle time 50 ns 4 notes 1. rxc is rxc or txc , whichever is supplying the receive clock. 2. txc is txc or rxc , whichever is supplyi ng the transmit clock. 3. parameter applies only to fm encoding/decoding. 4. clk is rxc or txc , when supplying dpll, brg, or ctr clock.
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 38 table 7 lists z16c30 system timing figure 26. z16c30 system timing 1 2 3 4 5 6 7 rxc , txc receive rxeq request int rxc as receiver output rxc , txc transmit txreq txc as transmitter output cts , dcd , txreq , rxreq note: clk is rxc or txc when supplying dpll, brg, or ctr clock.
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 39 architecture the usc internal structure includes two comple tely independent full- duplex serial chan- nels, each with two baud rate generators, a digital phase-locked loop for clock recovery, transmit and receive character counters and a full-duplex dma interface. the two serial channels share a common bus interface. the bu s interface is designed to provide easy interface to most microprocesso rs, whether they em ploy a multiplexed or nonmultiplexed, 8-bit or16-bit bus structure. each channel is co ntrolled by a set of thirty 16-bit registers, nearly all of which are readable and writable. there is one additional 16-bit register in the bus interface used to configur e the nature of the bus interface. the bcr functions are shown as follows: table 7. z16c30 system timing no symbol parameter min max units notes 1 tdrxc(req) rxc rise to rxreq valid delay 100 ns 1 2 tdrxc(rxc) txc rise to rxc as receiver output valid delay 100 ns 1 3 tdrxc(int) rxc rise to int valid delay 100 ns 1 4 tdtxc(req) txc fall to txreq valid delay 100 ns 2 5 tdtxc(txc) rxc fall to txc as transmitter output valid delay 100 ns 2 6 tdtxc(int) txc fall to int valid delay 100 ns 2 7 tdext(int) cts , dcd , txreq , rxreq transition to int valid delay 100 ns notes 1. rxc is rxc or txc , whichever is supplying the receive clock. 2. txc is txc or rxc , whichever is supplyi ng the transmit clock.
ds007902-0708 p r e l i m i n a r y electrical characteristics z16c30 product specification 40 figure 27. bus configuration register data path both the transmitter and the re ceiver in the channel are actually microcoded serial proces- sors. as the data shifts through the transm it or receive shift register, the microcode watches for specific bit patterns, counts bits, and at the appropriate time transfers data to or from the fifos. the microcode also check s status and generates status interrupts as appropriate. d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: none shift right addresses double-pulse intack 16-bit bus 0* reserved 3-state all pins separate address for 8-bit bus * must be programmed as 0.
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 41 functional description the functional capabilities of the usc are descr ibed from two different points of view: as a data communications device, it transmits and receives data in a wide variety of data communications protocols; as a microprocesso r peripheral, the usc offers such features as read/write registers, a flexible bus interfa ce, dma interface support, and vectored inter- rupts. data communications capabilities the usc provides two independ ent full-duplex channels pr ogrammable for use in any common data communication protocol. th e receiver and transmitter modes are com- pletely independent, as are the two channels. e ach receiver and transmitter is supported by a 32-byte deep fifo and a 16-bit message leng th counter. all mod es allow optional even, odd, mark or space parity. synchronous modes allow the choice of two 16-bit or one 32-bit crc polynomial. selection of from one to eight bits-per-character is available in both receiver and transmitter, inde pendently. error and status co nditions are carried with the data in the receive and transmit fifos to greatly reduce the cpu ov erhead required to send or receive a message. specific, appropriat ely timed interrupts are available to signal such conditions as overrun, parity error, fra ming error, end-of-frame , idle line received, sync acquired, transmit underrun, crc sent, cl osing sync/flag sent, abort sent, idle line sent, and preamble sent. in add ition, several useful internal signals such as receive fifo load, received sync, transmit fifo read and tran smission complete may be sent to pins for use by external circuitry. asynchronous mode? the receiver and transmitter can hand le data at a rate of 1/16, 1/ 32, or 1/64 the clock rate. the receiver reject s start bits less than one-half a bit time and will not erroneously assemble characters follo wing a framing error. the transmitter is capable of sending one, two, or anywhere in the range of 1/16 to two stop bits per charac- ter in 1/16 bit increments. external sync mode? the receiver is synchronized to the receive data stream by an externally-supplied signal on a pin for custom protocol applications. isochronous mode? both transmitter and receiver may ope rate on start-stop (async) data using a 1x clock. the transmitter can send one or two stop bits. asynchronous with code violations? this is similar to isochr onous mode except that the start bit is replaced by a three bit-time code violation pattern as in mil-std 1553b. the transmitter can send zero, one or two stop bits. monosync mode? in this mode, a single character is used for synchronization. the sync character can be either eight bits long with an arbitrary data character length, or pro- grammed to match the data ch aracter length. the receiver is capable of automatically stripping sync characters from the receive d data stream. the transmitter may be pro-
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 42 grammed to automatically send crc on either an underrun or at the end of a programmed message length. bisync mode? this mode is identical to monosync mode except that character synchroni- zation requires two successive characters for synchronization. the two characters need not be identical. hdlc mode? in this mode, the receiver recognizes flags, performs optional address matching, accommodates extended address fields , 8- or 16-bit control fields and logical control fields, performs zero deletion and crc checking. the receiver is capable of receiving shared-zero flags, recognizes the ab ort sequence and can receive arbitrary length messages. the transmitter automatically sends opening and closing flags, performs zero insertion and can be programmed to send an abor t, an extended abort, a flag or crc, and a flag on transmit underrun. the transmitter can also automatically send the closing flag with optional crc at the end of a programm ed message length. shared-zero flags are selected in the transmitter and a separate char acter length may be programmed for the last character in the frame. bisync transparent mode? in this mode, the synchronizat ion pattern is dle?syn, pro- grammable selected from either ascii or ebcdic encoding. the receiver recognizes control character sequences and automatica lly handles crc calculation without cpu intervention. the transmitter can be progra mmed to send either syn, dle?syn, crc? syn, or crc?dle?syn upon und errun and can automatically send the closing dle? syn with optional crc at the end of a programmed message length. nbip mode? this mode is identical to async except that the receiver checks for the status of an additional address/data bit between the pa rity bit and the stop bit. the value of this bit is fifo?ed along with the da ta. this bit is automatically in serted in the transmitter with the value that is fifo?e d with the transmit data. 802.3 mode? this mode implements the data form at of ieee 802.3 w ith 16-bit address compare. in this mode, dcd and cts are used to implement the carrier sense and colli- sion detect interactions with the receiver and transmitter. slaved monosync mode? this mode is available only in the transmitter and allows the transmitter (operating as though it were in monosync mode) to send data that is byte-syn- chronous to the data being received by the receiver. hdlc loop mode? this mode is also available only in the transmitte r and allows the usc to be used in an hdlc loop configuratio n. in this mode, the receiver is programmed to operate in hdlc mode so that the transmitter echoes rece ived messages. upon receipt of a particular bit pattern (actually a seque nce of seven consecutiv e ones) the transmitter breaks the loop and inserts its own frame(s). data encoding the usc may be programmed to encode and dec ode the serial data in any of eight differ- ent ways as displayed in figure 28 on page 44. the transmitter encoding method is selected independently of the receiver decoding method.
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 43 nrz? in nrz, a 1 is represented by a high leve l for the duration of the bit cell and a 0 is represented by a low level for the duration of the bit cell. nrzb? data is inve rted from nrz. nrzi-mark? in nrzi-mark, a 1 is represented by a transition at the beginning of the bit cell. that is, the level present in the preceding bit cell is reversed. a 0 is represented by the absence of a transition at the beginning of the bit cell. nrzi-space? in nrzi-space, a 1 is represented by the absence of a transition at the beginning of the bit cell. that is, the level present in the pre ceding bit cell is maintained. a 0 is represented by a transition at the beginning of the bit cell. biphase-mark? in biphase-mark, a 1 is represented by a transition at the beginning of the bit cell and another transition at the center of the bit cell. a 0 is re presented by a transition at the beginning of the bit cell only. biphase-space? in biphase-space, a 1 is represented by a transition at the beginning of the bit cell only. a 0 is represented by a tr ansition at the beginning of the bit cell and another transition at the center of the bit cell. biphase-level? in biphase-level, a 1 is represented by a high during the first half of the bit cell and a low during the second half of the bit cell. a 0 is represented by a low dur- ing the first half of the bit cell and a high during the second half of the bit cell.
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 44 differential biphase-level? in differential biphase-level, a 1 is represented by a transi- tion at the center of the bit cell, with the oppo site polarity from the transition at the center of the preceding bit cell. a 0 is represented by a transition at the center of the bit cell with the same polarity as the transition at the center of the preceding bit cell. in both cases there may be transitions at the beginn ing of the bit cell to set up the level required to make the correct center transition. character counters each channel in the usc contains a 16-bit ch aracter counter for both receiver and trans- mitter. the receive character co unter may be preset either under software control or auto- matically at the beginning of a receive messag e. the counter decremen ts with each receive character and at the end of th e receive message the current value in the counter is automat- figure 28. data encoding data110010 nrz nrzb nrzi-m nrzi-s bi-phase-m biphase-s biphase-l differential biphase-l
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 45 ically loaded into a four-deep fifo. this allo ws dma transfer of data to proceed without cpu intervention at the end of a received me ssage, as the values in the fifo allow the cpu to determine message boundaries in memory. similarly, the transmit character counter is loaded either under software cont rol or automatically at the beginning of a transmit message. the counter is decremented with each write to the transmit fifo. when the counter has decremented to 0, and that byte is sent, the transmitter automatically termi- nates the message in the appropriate fashion (usually crc and the cl osing flag or sync character) without requiring cpu intervention. baud rate generators each channel in the usc contains two baud ra te generators. each ge nerator consists of a 16-bit time constant register and a 16-bit down counter. in operation, the counter decre- ments with each baud rate generator clock, with the time constant automatically reloaded when the count reaches zero. the output of th e baud rate generator toggles when the counter reaches a count of one-half of th e time constant and again when the counter reaches zero.a new time constant may be written at any tim e but the new value will not take effect until the next load of the counter. the outputs of both baud rate generators are sent to the clock multiplexer for use internally or externally. the baud rate generator out- put frequency is related to the baud rate ge nerator input clock frequ ency by the following equation: output frequency = input fre quency/(time constant + 1) this allows an output frequency in the range of 1 to 1/65536 of the input frequency, inclu- sive. digital phase-locked loop each channel in the usc contains a digita l phase-locked loop (dpll) to recover clock information from a data stream with nrzi or biphase encoding. the dpll is driven by a clock that is nominally 8, 16 or 32 times the receive data rate. the dpll uses this clock, along the data stream, to construct a clock for the data. this clock may then be routed to the receiver, transmitter, or both, or to a pin for use externally. in all modes, the dpll counts the input clock to create nominal bi t times. as the clock is counted, the dpll watches the incoming data stream for transiti ons. whenever a trans ition is detected, the dpll makes a count adjustment (during the ne xt counting cycle), to produce an output clock which tracks the incoming bit cells. the dpll provides properly phased transmit and receive clocks to the clock multiplexer. counters each channel contains two 5-bit counters, which are programmed to divide an input clock by 4, 8, 16, or 32. the inputs of these two counters are sent to th e clock multiplexer. the counters are used as prescalers for the baud ra te generators, or to provide a stable transmit clock from a common source when the dpll is providing the receive clock.
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 46 clock multiplexer the clock multiplexer in each channel selects the clock source for the various blocks in the channel and selects an internal clock signal to potentially be sent to either the rxc or txc pin. test modes the usc can be programmed for local loopback or auto echo operation. in local loopback, the output of the transmitter is internally routed to the input of the receiver. this allows testing of the usc data paths without any exte rnal logic. auto echo connects the rxd pin directly to the txd pin. this is useful for testing serial links external to the usc. i/o interface capabilities the usc offers the choice of polling, interrupt (vectored or nonvecto red) and block trans- fer modes to transfer data, status and control information to and from the cpu. polling all interrupts are disabled. the registers in the usc are automatically updated to reflect current status. the cpu polls the daisy chain control register (dccr) to determine sta- tus changes and then reads the appropriate status register to find and respond to the change in status. usc status bits are grouped acco rding to function to si mplify this software action. interrupt when a usc responds to an interrupt acknowledge from the cpu, an interrupt vector may be placed on the data bus. this vector is he ld in the interrupt vector register (ivr). to speed interrupt response time, th e usc modifies three bits in th is vector to indicate which type of interrupt is being requested. each of the six sources of interrupts in each channel of the usc (receive status, receive data, transmit status, transmit data, i/o stat us, and device status) has three bits associ- ated with the interrupt source: interrupt pe nding (ip), interrupt-under-service (ius), and interrupt enable (ie). if the ie bit for a given source is set, that source can request inter- rupts. note that individual sources within the six groups also have interrupt enable bits which are set for the particular source. in ad dition, there is a master interrupt enable (mie) bit in each channel which globally enab les or disables interrupts within the channel. the other two bits are related to the interrupt priority chai n. a channel in the usc may request an interrupt only when no higher prio rity interrupt source is requesting one, e.g., when iei is high for the channel. in this case the channel activates the int signal. the cpu then responds with an interrupt ackn owledge cycle, and th e interrupting channel places a vector on the data bus.
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 47 in the usc, the ip bit signals th at an interrupt request is being serviced. if an ius is set, all interrupt sources of lower priority within the channel and external to the channel are pre- vented from requesting interrupts. the internal interrupt sources are inhibited by the state of the internal daisy chain, while lower prior ity devices are inhibited by the ieo output of the channel being pulled low and propagated to subsequent peripherals. an ius bit is set during an interrupt acknowledge cycle if th ere are no higher priority devices requesting interrupts. there are six sources of interrupt in each ch annel: receive status, receive data, transmit status, transmit data, i/o status, and device st atus, prioritized in that order within the channel. there are six sources of receive st atus interrupt, each individually enabled: exited hunt, idle line, break/abort, code viol ation/end-of-transmissi on/end-of-frame, parity error, and overrun error. the receive data interrupt is generated whenever the receive fifo fills with data beyond the level progra mmed in the receive interrupt control regis- ter (ricr). there are six sources of transmit status in terrupt, each individually enabled: preamble sent, idle line sent, abort sent, end-of-fra me/end-of-transmission sent, crc sent, and underrun error. the transmit data interrupt is generated whenever the transmit fifo empties below the level program med in the transmit interrupt control register (ticr). the i/o status interrupt serves to report transitions on any of six pins. interrupts are gener- ated on either or both edges with separate sel ection and enables for each pin. the pins pro- grammed to generate i/o status interrupts are rxc , txc , rxreq , txreq , dcd, and cts . these interrupts are independent of the programmed function of the pins. the device status interrupt has four separately en abled sources: receive character count fifo overflow, dpll sync acquired, brg1 zero count, and brgo zero count. block transfer mode the usc accommodates block transf ers through dma through the rxreq , txreq , rxack, and txack pins. the rxreq signal is activated when the fill level of the receive fifo exceeds the value programmed in the ricr. the dma may respond with either a normal bus transactio n or by activating the rxack pin to read th e data directly (fly-by transfer). the txreq signal is activated when th e empty level of the transmit fifo falls below the value programmed in th e ticr. the dma may respond either with a normal bus transaction or by activating the txack pin to write the data directly (fly-by transfer). the rxack and txack pin functions for this mode are controlled by the hard- ware configuration register (hcr). then using the rxack and txack pins to transfer data, no chip select is necessary; these are dedicated strobes for the appropriate fifo. programming the registers in each usc channel are programm ed by the system to configure the chan- nels. before this can occur, however, the system must program the bus interface by writing to the bus configuration re gister (bcr). the bcr has no specific address and is only
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 48 accessible immediately after a hardware reset of the device. the first write to the usc, after a hardware reset, programs the bcr. from that time on, the norm al channel registers may be accessed. no sp ecific address need be presen ted to the usc for the bcr write because the first write after a hardware rese t is automatically programmed for the bcr. in the multiplexed bus case, all registers ar e directly addressable through the address latched by as at the beginning of a bus transactio n. the address is decoded from either ad6?ad0 or ad7?ad1. this is controlled by the shift right/shift left bit in the bcr. the address maps for these two cases are listed in table 8 . the d/c pin is still used to directly access the receive an d transmit data registers (rdr and tdr) in the multiplexed bus; if d/c is high the address latched by as is ignored and an access of rdr or tdr is performed. in the nonmultiplexe d bus case, the registers in each ch annel are accessed indirectly using the address pointer in the ch annel command/address register (ccar) in each channel. the address of the desired register is first written to the ccar and then the selected regis- ter is accessed; the pointer in the ccar is automatically cleared after this access. the rdr and tdr are accessed directly using the d/c pin, without disturbing the contents of the pointer in the ccar. 1. the channel reset bit in the ccar places the channel in the reset state. to exit this reset state either a word of all zeros must be written to the ccar (16-bit bus), or a byte of all zeros must be written to the lower byte of the ccar (8-bit bus). 2. after reset, the transmit and receive cloc ks are not connected. the first thing that should be done in any initia lization sequence is a write to the clock mode control register (cmcr) to select a clock so urce for the receiver and transmitter. the register addressing is listed in table 9 on page 50 while the bit assignments for the registers are displayed in figure 29 . table 8. multiplexed bus address assignments address signal shift left shift right byte/word access ad7 ad6 address 4 ad6 ad5 address 3 ad5 ad4 address 2 ad4 ad3 address 1 ad3 ad2 address 0 ad2 ad1 upper/lower byte select ad1 ad0 notes:
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 49 figure 29. bcr reset sequence and bit assignments reset multiplexed bus at least one as no as any transaction up t o and including bcr w rite bcr write transaction 8-bit with separate address 8-bit without separate address 16-bit bcr[2]=0 bcr[15]=1 bcr[2]=0 bcr[15]=0 bcr[2]=1 note: the presence of one transaction with an /as active between reset, up to and including the bcr write, chooses a multiplexed type of bus. non-multiplexed bus 8-bit with separate address 8-bit without separate address 16-bit bcr[2]=0 bcr[15]=1 bcr[2]=0 bcr[15]=0 bcr[2]=1
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 50 table 9. register address list address a4?a0 00000 ccar channel command/address register 00001 cmr channel mode register 00010 ccsr channel command/status register 00011 ccr channel control register 00110 tmdr test mode data register 00111 tmcr test mode control register 01000 cmcr clock mode control register 01001 hcr hardware configuration register 01010 ivr interrupt vector register 01011 iocr i/o control register 01100 icr interrupt control register 01101 dccr daisy-chain control register 01110 misr misc interrupt status register 01111 sicr status interrupt control register 1x000 rdr receive data register (read only) 10001 rmr receive mode register 10010 rcsr receive command/status register 10011 ricr receive interrupt control register 10100 rsr receive sync register 10101 rclr receive count limit register 10110 rccr receive character count register 10111 tc0r time constant 0 register 1x000 tdr transmit data register (write only) 11001 tmr transmit mode register 11010 tcsr transmit command/status register 11011 ticr transmit inte rrupt control register 11100 tsr transmit sync register 11101 tclr transmit count limit register 11110 tccr transmit character count register 11111 tc1r time constant 1 register xxxxx bcr bus config uration register
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ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 52 figure 31. channel mode register 0 0 0 0 asynchronous 0 0 0 1 external synchronous 0 0 1 0 isochronous 0 0 1 1 asynchronous with cv 0 1 0 0 monosync 0 101 bisync 0 110 hdlc 0 1 1 1 transparent bisync 1 000 nbif 1 0 0 1 802.3 1 010 reserved 1 011 reserved 1 100 reserved 1 101 reserved 1 110 reserved 1 111 reserved receive mode rx submode 0 rx submode 1 rx submode 2 rx submode 3 0000 0001 0010 0011 0100 01 01 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 asynchronous reserved isochronous asynchronous with cv monosync bisync hdlc transparent bisync nbip 802.3 reserved reserved slaved monosync reserved hdlc loop reserved transmitter mode tx submode 0 tx submode 1 tx submode 2 tx submode 3 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 53 figure 32. channel mode register, asynchronous mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 0 0 0 0 asynchronous receiver mode 0 0 16x data rate 0 1 32x data rate 1 0 64x data rate 11 reserved rx clock rate reserved reserved 0 0 0 0 asynchronous transmitter mode 0 0 16x data rate 0 1 32x data rate 1 0 64x data rate 11 reserved tx clock rate 00 one stop bit 0 1 two stop bits 1 0 one sop bit, shared 1 1 two stop bits, shared tx stop bits
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 54 figure 33. channel mode register, external sync mode figure 34. channel mode register, isochronous mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode transmitter mode 00 0 1 00 0 1 external sync reserved reserved reserved d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 0010 0010 receiver isochronous mode transmitter isochronous mode reserved tx two stop bits reserved reserved
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 55 figure 35. channel mode register, asynchronous mode with code violation (mil std 1553) d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 0 0 1 1 asynchronous with cv receiver mode rx extended word reserved 0000 asynchronous with cv transmitter mode cv polarity tx extended word 0 0 one stop bit 0 1 two stop bits 1 0 no stop bit 1 1 reserved tx stop bits
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 56 figure 36. channel mode register, monosync mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 0 0 1 0 monosync 0 0 1 0 monosync transmitter mode rx short sync character rx sync strip reserved tx short sync character tx preamble enable reserved tx crc on underrun
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 57 figure 37. channel mode register, bisync mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 0101 bisync 0101 bisync transmitter mode rx short sync character rx sync strip reserved tx short sync character tx preamble enable 0 0 syn1 0 1 syn0/syn1 1 0 crc/syn1 1 1 crc/syn0/syn1 tx underrun condition
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 58 figure 38. channel mode register, hdlc mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 0 1 1 0 hdlc 0110 hdlc transmitter mode shared zero flags tx preamble enable 00 abort 0 1 extended abort 10 flag 1 1 crc/flag tx underrun condition 00 disabled 0 1 one byte, no control 1 0 one byte, plus control 1 1 extended, plus control rx address search mode rx 16-bit control rx logical control enable
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 59 figure 39. channel mode register, transparent bisync mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 0111 transparent bisync 0111 transparent bisync transmitter mode ebcdic reserved ebcdic tx preamble enable 00 syn 0 1 dle/syn 1 0 crc/syn 1 1 crc/dle/syn tx underrun condition
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 60 figure 40. channel mode register, nbip mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 100 0 nbip 1000 nbip transmitter mode 0 0 16x data rate 0 1 32x data rate 1 0 64x data rate 11 reserved rx parity on data reserved 0 0 16x data rate 0 1 32x data rate 1 0 64x data rate 11 reserved tx parity on data tx address bit tx clock rate
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 61 figure 41. channel mode register, 802.3 mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 1 0 0 1 802.3 1 0 0 1 802.3 transmitter mode rx address search reserved tx crc on underrun reserved
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 62 figure 42. channel mode register, slaved monosync mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 110 0 reserved 1 1 0 0 slaved monosync transmitter mode reserved reserved tx short sync character tx active on received sync tx crc on underrun
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 63 figure 43. channel mode register, hdlc loop mode d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00001 receiver mode 1110 reserved 1 1 1 0 hdlc loop shared zero flags tx active on poll 00 abort 0 1 extended abort 10 flag 1 1 crc/flag tx underrun condition reserved transmitter mode
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 64 figure 44. channel command/status register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00010 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits 1 1 0 6 bits 111 7 bits 0 0 both edges 0 1 rising edge only 1 0 falling edge only 1 1 adjust/sync input dpll adjust/ sync edge hdlc tx last character length reserved loop sending (r0) on loop (r0) clock missed latched/unlatch clocks missed latched/unlatch dpll in sync/quick sync rcc fifo clear (w0) rcc fifo valid (r0) rcc fifo overflow (r0) rxack (r0) txack (r0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 65 figure 45. channel control register figure 46. primary reserved register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00011 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 64 bits tx preamble length 0 0 all zeros 0 1 all ones 1 0 alternating 1 and 0 1 1 alternating 0 and 1 tx preamble pattern 00no status block 0 1 one word status block 1 0 two word status block 11 reserved rx status block transfer reserved wait for rx dma trigger (all sync) tx flag preamble wait for tx dma trigger tx shaved bit length (async only) 00no status block 0 1 one word status block 1 0 two word status block 11 reserved tx status block transfer d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00100 reserved
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 66 figure 47. secondary reserved register figure 48. test mode data register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00101 reserved d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00110 test data <0> test data <1> test data <2> test data <3> test data <4> test data <5> test data <6> test data <7> test data <8> test data <9> test data <10> test data <11> test data <12> test data <13> test data <14> test data <15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 67 figure 49. test mode control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 00111 0 0 0 0 0 null address 0 0 0 0 1 high byte of shifters 00 010crc byte 0 00 011crc byte 1 0 0 1 0 0 rx fifo (write) 0 0 1 0 1 clock multiplexer outputs 0 0 1 1 0 ctr0 and ctr1 counters 0 0 1 1 1 clock multiplexer inputs 01 000dpll status 0 1 0 0 1 low byte of shifters 01 010crc byte 2 01 011crc byte 3 0 1 1 0 0 tx fifo (read) 0 1 1 0 1 reserved 0 1 1 1 0 i/o and device status latches 0 1 1 1 1 internal daisy chain 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 reserved 1 0 1 0 1 reserved 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 4044h 1 1 0 0 1 4044h 1 1 0 1 0 4044h reserved test register address
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 68 figure 50. clock mode control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01000 000 disabled 0 0 1 rxc pin 0 1 0 txc pin 0 1 1 dpll output 1 0 0 brg0 output 1 0 1 brg1 output 1 1 0 ctr0 output 1 1 1 ctr1 output 0 0 0 disabled 0 0 1 rxc pin 0 1 0 txc pin 0 1 1 dpll output 1 0 0 brg0 output 1 0 1 brg1 output 110ctr0 output 1 1 1 ctr1 output 00 ctr0 output 01 ctr1 output 1 0 rxc pin 11 txc pin 0 0 brg0 output 0 1 brg1 output 1 0 rxc pin 11 txc pin 0 0 ctr0 output 0 1 ctr1 output 1 0 rxc pin 11 txc pin 00 disabled 01 disabled 1 0 rxc pin 11 txc pin 00 disabled 01 disabled 1 0 rxc pin 11 txc pin ctr1 clock source ctr0 clock source brg1 clock source brg0 clock source dpll clock source transmit clock source receive clock source
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 69 figure 51. hardware configuration register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01000 00 disabled 01 nrz/nrzi 1 0 biphase-mark/space 1 1 biphase-level 0 0 32x clock mode 0 1 16x clock mode 1 0 8x clock mode 1 1 4x clock mode txack pin control ctr0 clock rate dpll clock rate dpll mode brg0 enable brg0 single cycle/continuous 0 0 3-state output 0 1 rx acknowledge input 1 0 output 0 1 0 output 1 brg1 enable brg1 single cycle/continuous 0 0 3-state output 0 1 tx acknowledge input 1 0 output 0 1 0 output 1 0 0 32x clock mode 0 1 16x clock mode 1 0 8x clock mode 11 reserved rxack pin control accept code violations ctr1 rate match dpll/ctr0
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 70 figure 52. interrupt vector register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01010 iv<0> iv<1> iv<2> iv<3> iv<4> iv<5> iv<6> iv<7> iv<0>(r0) iv<4>(r0) iv<5>(r0) iv<6>(r0) iv<7>(r0) 000 none 0 0 1 device status 0 1 0 i/o status 0 1 1 transmit data 1 0 0 transmit status 1 0 1 receive data 1 1 0 receive status 1 1 1 not used modified vector (r0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 71 figure 53. i/o control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01001 0 0 0 input pin 0 0 1 rx clock output 0 1 0 rx byte clock output 0 1 1 sync output 1 0 0 brg0 output 1 0 1 brg1 output 1 1 0 ctr0 output 1 1 1 dpll rx output 000 input pin 0 0 1 tx clock output 0 1 0 tx byte clock output 0 1 1 tx complete output 1 0 0 brg0 output 1 0 1 brg1 output 110 ctr0 output 111 dpll output 0 0 3-state output 0 1 rx request output 1 0 output 0 1 1 output 1 0 0 tx data output 0 1 3-state output 10 output 0 11 output 1 0 0 3-state output 0 1 tx request output 1 0 output 0 1 1 output 1 0 0 dcd input 0 1 dcd/sync input 1 0 output 0 1 1 output 1 0 0 cts input 0 1 cts input 1 0 output 0 1 1 output 1 cts pin control dcd pin control txreq pin control rxreq pin control txd pin control txc pin control rxc pin control
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 72 figure 54. interru pt control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01100 device status ie i/o status ie transmit data ie transmit status ie receive data ie receive status ie received vis nv dlc mie 000 all 001 all 0 1 0 i/o status and above 0 1 1 transmit data and above 1 0 0 transmit status and above 1 0 1 receive data 1 1 0 receive status only 1 1 1 none vis level 0 0 null command 0 1 null command 10 reset ie 11 set ie ie command (w0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 73 figure 55. daisy-chain control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01101 device status ip i/o status ip transmit data ip transmit status ip receive data ip receive status ip device status ius i/o status ius transmit data ius transmit status iu s receive data ius 0 0 null command 0 1 reset ip and ius 10 reset ip 11 set ip ip command (w0) 0 0 null command 0 1 null command 10 reset ius 11 set ius ius command (w0) receive status ius
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 74 figure 56. miscellaneous interrupt status register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01110 brg0 zc latched/unlatch brg1 zc latched/unlatch dpll sync latched/unlatch rcc overflow latched/unlatch cts (r0) cts latched/unlatch dcd (r0) dcd latched/unlatch txreq (r0) txreq latched/unlatch rxreq (r0) rxreq latched/unlatch txc (r0) txc latched/unlatch rxc (r0) rxc latched/unlatch
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 75 figure 57. status in terrupt control register 00 disabled 0 0 rising edge only 0 1 falling edge only 0 1 both edges cts interrupts dcd interrupts 00 disabled 0 0 rising edge only 0 1 falling edge only 01 both edges txreq interrupts 00 disabled 0 0 rising edge only 0 1 falling edge only 0 1 both edges 00 disabled 0 0 rising edge only 0 1 falling edge only 01 both edges rxreq interrupts txc interrupts 00 disabled 0 0 rising edge only 0 1 falling edge only 0 1 both edges rxc interrupts brg0 zc ie brg1 zc ie dpll sync ie rcc overflow ie 00 disabled 0 0 rising edge only 0 1 falling edge only 0 1 both edges d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 01111
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 76 figure 58. receive data register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 0x110 rx dat <0>(r0) rx dat <1>(r0) rx dat <2>(r0) rx dat <3>(r0) rx dat <4>(r0) rx dat <5>(r0) rx dat <6>(r0) rx dat <7>(r0) rx dat <8>(r0) rx dat <9>(r0) rx dat <10>(r0) rx dat <11>(r0) rx dat <12>(r0) rx dat <13>(r0) rx dat <14>(r0) rx dat <15>(r0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 77 figure 59. receive mode register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10001 0 0 disable immediately 0 1 disable after reception 1 0 enable without auto-enables 1 1 enable with auto-enable rx enable 0 0 0 8 bits 001 1 bit 0 1 0 2 bits 0 1 1 3 bits 1 0 0 4 bits 1 0 1 5 bits 1 1 0 6 bits 1 1 1 7 bits rx character length 00 even 01 odd 1 0 space 11 mark rx parity sense 0 0 crc-ccitt 0 1 crc-16 1 0 crc-32 11 reserved rx crc polynomial 000 nrz 0 0 1 nrzb 0 1 0 nrzi-mark 0 1 1 nrzi-space 1 0 0 biphase-mark 1 0 1 biphase-space 1 1 0 biphase-level 1 1 1 diff. biphase-level rx data decoding queue abort rx crc enable rx crc preset value
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 78 figure 60. receive command status register 0000null command 0001reserved 0 0 1 0 preset crc 0 0 1 1 enter hunt mode 0100reserved 0 1 0 1 select fifo status 0 1 1 0 select fifo interrupt level 0 1 1 1 select fifo status level 1000reserved 1001reserved 1010reserved 1011reserved 1100reserved 1101reserved 1110reserved 1111reserved d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10010 receive command (r0) first byte in error (r0) second byte in error (r0) rx character available (r0) rx overrun parity error/frame abort crc/framing error rx cv/eot/eof rx break/abort rx idle exited hunt short frame/cv polarity (r0) residue code 0 (r0) residue code 1 (r0) residue code 2 (r0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 79 figure 61. receive interrupt control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10011 tc0r read count/tc rx overrun ia parity error/frame abort ia status on words rx cv/eot/eof ia rx break/abort ia rx idle ia exited hunt ia rx fifo control and status (fill/interrupt/dma level)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 80 figure 62. receive sync register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10100 rsyn<0> rsyn<1> rsyn<2> rsyn<3> rsyn<4> rsyn<5> rsyn<6> rsyn<7> rsyn<8> rsyn<9> rsyn<10> rsyn<11> rsyn<12> rsyn<13> rsyn<14> rsyn<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 81 figure 63. receive count limit register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10101 rcl<0> rcl<1> rcl<2> rcl<3> rcl<4> rcl<5> rcl<6> rcl<7> rcl<8> rcl<9> rcl<10> rcl<11> rcl<12> rcl<13> rcl<14> rcl<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 82 figure 64. receive character count register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10110 rcc<0> (r0) rcc<1>(r0) rcc<2>(r0) rcc<3>(r0) rcc<4>(r0) rcc<5>(r0) rcc<6>(r0) rcc<7>(r0) rcc<8>(r0) rcc<9>(r0) rcc<10>(r0) rcc<11>(r0) rcc<12>(r0) rcc<13>(r0) rcc<14>(r0) rcc<15>(r0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 83 figure 65. time constant 0 register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 10111 tc0<0> tc0<1> tc0<2> tc0<3> tc0<4> tc0<5> tc0<6> tc0<7> tc0<8> tc0<9> tc0<10> tc0<11> tc0<12> tc0<13> tc0<14> tc0<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 84 figure 66. transmit data register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 1x000 txdat<0>(w0) txdat<1>(w0) txdat<2>(w0) txdat<3>(w0) txdat<4>(w0) txdat<5>(w0) txdat<6>(w0) txdat<7>(w0) txdat<8>(w0) txdat<9>(w0) txdat<10>(w0) txdat<11>(w0) txdat<12>(w0) txdat<13>(w0) txdat<14>(w0) txdat<15>(w0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 85 figure 67. transmit mode register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11001 0 0 disable immediately 0 1 disable after reception 1 0 enable without auto-enables 1 1 enable with auto-enable tx enable 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits 1 1 0 6 bits 111 7 bits rx character length 0 0 even 01 odd 1 0 space 11 mark tx parity sense 0 0 crc-ccitt 0 1 crc-16 1 0 crc-32 1 1 reserved tx crc polynomial 000 nrz 0 0 1 nrzb 0 1 0 nrzi-mark 0 1 1 nrzi-space 1 0 0 biphase-mark 1 0 1 biphase-space 1 1 0 biphase-level 1 1 1 diff. biphase-level tx data decoding tx crc on eof/eom tx crc enable tx crc preset value tx parity enable
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 86 figure 68. transmit command/status register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11010 0000null command 0001reserved 0010preset crc 0 0 1 1 enter hunt mode 0100reserved 0 1 0 1 select fifo status 0 1 1 0 select fifo interrupt level 0 1 1 1 select fifo status level 1000 send frame message 1001 send abort 1010 reserved 1011 reserved 1100 reset dle inhibit 1101 set dle inhibit 1110 reset eof/eom 1111 set eot/eom 0 0 0 null command 0 0 0 reserved 0 1 0 preset crc 0 1 1 enter hunt mode 1 0 0 reserved 1 0 1 select fifo status 1 1 0 select fifo interrupt level 1 1 1 select fifo status level tx buffer empty (r0) tx underrun all sent (r0) tx crc sent tx eof/eot sent tx abort sent tx idle sent tx preamble sent tx idle line condition tx wait on underrun transmit command (w0)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 87 figure 69. transmit interrupt control register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11011 tc1r read count/tc tx overrun ia wait for send command tx crc sent ia tx eof/eot sent ia tx abort sent ia tx idle sent ia tx preamble sent ia tx fifo control and status (fill/interrupt/dma level)
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 88 figure 70. transmit sync register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11100 tsyn<0> tsyn<1> tsyn<2> tsyn<3> tsyn<4> tsyn<5> tsyn<6> tsyn<7> tsyn<8> tsyn<9> tsyn<10> tsyn<11> tsyn<12> tsyn<13> tsyn<14> tsyn<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 89 figure 71. transmit count limit register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11101 tcl<0> tcl<1> tcl<2> tcl<3> tcl<4> tcl<5> tcl<6> tcl<7> tcl<8> tcl<9> tcl<10> tcl<11> tcl<12> tcl<13> tcl<14> tcl<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 90 figure 72. transmit character count register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11110 tcc<0> tcc<1> tcc<2> tcc<3> tcc<4> tcc<5> tcc<6> tcc<7> tcc<8> tcc<9> tcc<10> tcc<11> tcc<12> tcc<13> tcc<14> tcc<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 91 figure 73. time constant 1 register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: 11111 tc1<0> tc1<1> tc1<2> tc1<3> tc1<4> tc1<5> tc1<6> tc1<7> tc1<8> tc1<9> tc1<10> tc1<11> tc1<12> tc1<13> tc1<14> tc1<15>
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 92 figure 74. receive status block register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: none* rcc<0> rx overrun parity error/frame abort crc error rx cv/eot/eof rcc fifo overflow 0 0 short frame/cv polarity residue code 0 residue code 1 residue code 2 0 0 first byte in error second byte in error * refer to figure 22, channel control register bits 6?7 for access method
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 93 figure 75. transmit status block register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: none* * refer to figure 22, channel control register bits 6?7 for access method 0008 bits 0001 bit 0102 bits 0113 bits 1004 bits 1015 bits 1106 bits 1117 bits hdlc tx last character length reserved reserved tx submode 1 tx submode 2 tx submode 3 tx submode 0
ds007902-0708 p r e l i m i n a r y functional description z16c30 product specification 94 figure 76. bus configuration register d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 address: none shift right addresses double-pulse intack 16-bit bus 0* reserved 3-state all pins separate address for 8-bit bus *must be programmed as zero.
ds007902-0708 p r e l i m i n a r y packaging z16c30 product specification 95 packaging figure 77 displays the 68-pin plcc package diagram. figure 77. 68-pin plcc package diagram
ds007902-0708 p r e l i m i n a r y packaging z16c30 product specification 96 figure 78 displays 100-pin vqfp package diagram figure 78. 100-pin vqfp package diagram
ds007902-0708 p r e l i m i n a r y ordering information z16c30 product specification 97 ordering information order the z16c30 series from zilog ? , using the following part numbers. for more infor- mation on ordering, consult your local zilog sales office. the zilog website ( www.zilog.com ) lists all regional offices and prov ides additional z16c 30 product infor- mation. for fast results, contact your local zilog ? sales office for assistance in ordering the part desired. codes z16c30 (10 mhz) 68-pin plcc z16c3010vsc z 16c30 10 v s c environmental flow c= plastic standard flow temperature range s = 0 c to 70 c (standard) package v= plastic leaded chip carrier speed 10= 10 mhz product number 16c30 zilog ? prefix
ds007902-0708 p r e l i m i n a r y customer support z16c30 product specification 98 customer support for answers to technical questions about the product, documenta tion, or any other issues with zilog?s offe rings, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questi ons, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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